1. Field of the Invention
The present disclosure relates to a memory controller, a flash memory system and a method controlling a flash memory device, and particularly, to such a memory controller and a flash memory system that can perform a series of data write operations to a flash memory device fast and a method for perform a series of data write operations to a flash memory device fast.
2. Description of the Related Art
In recent years, flash memory devices, particularly NAND type flash memory devices, are widely used as semiconductor memory devices for memory cards, silicon disks and the like. In such a NAND type flash memory device, although a transition from an erased state (logical value=“1”) to a programmed state (logical value=“0”) can be performed for each memory cell as an individual unit, a transition from the programmed state (0) to the erased state (1) cannot be performed for each memory cell as an individual unit. Such a transition from the programmed state (0) to the erased state (1) can be only performed for a predetermined number of memory cells as a unit, called a “block”, constituted of a plurality of memory cells. Such an operation is called “block erasing”.
According to the NAND type flash memory device, because the transition from the programmed state (0) to the erased state (1) cannot be performed for each memory cell as an individual unit, in order to write data into a certain block, it is required to perform a block erasing operation to change the states of all memory cells included in the block to the erased state (1). A block-erased block becomes a free block in which no data are stored. In order to write new data into a flash memory device, search is made for such a free block and the new data are written into a found free block. Each block is constituted of a plurality of “pages” each of which is an access unit for a data reading and a data writing.
The data writing for the flash memory device is performed as follows:
First, when a data writing request is issued from a host computer and the address and the data to be written are transferred, the data is temporarily stored into a buffer memory employed in a controller. Then, the controller transfers the data temporarily stored in the buffer memory to the flash memory device and requests the flash memory device to store it into the page designated by the address. Responsive to it, the flash memory device stores the data transferred from the controller into the designated page. The data write operation is then completed.
The host computer treats the pages in the same block as assigned the successive addresses by ordinary. Most of the data writing request from the host computer are directed to a plurality of successive addresses. In this case, it is necessary for the controller to write data successively to the plurality of successive pages in certain block.
Specifically, the controller transfers the data to be stored in the first page to the flash memory device and requests the flash memory device to store the data into this page. When the flash memory device stores the transferred data into the designated page in response to the operation, the controller transfers the data to be stored in the next page to the flash memory device and requests the flash memory device to store the data into this page. When such operations are successively performed for the plurality of requested addresses, a series of data write operations for the plurality of successive addresses is completed.
The data write operation for one page requires a predetermined operation time which is constituted of the time for transmitting the data to be stored from the controller to the flash memory device (data transmission period), the time for issuing a data write command from the controller to the flash memory device (command issuing period), the time for actually storing the data into the flash memory device (flash programming period), and so forth; the flash programming period is particularly long time (about 200 μsec for example).
According to the prior art, when the data write request for the plurality of successive addresses is issued from the host computer, a time substantially in proportion to the number of pages into which the data are to be stored is required to complete a series of data write operations because the unit of data write operation which requires relatively long time should be successively performed.
Thus, it has been desired that a memory controller, a flash memory system and a method for controlling a flash memory device can perform a series of data write operations fast when the data write request for the plurality of successive addresses is issued from the host computer.